Combinatorial logic devices produce one or more output signals in response to logical combinations of one or more input signals. Thus, combinatorial networks can function to indicate the presence of a given set of input signals by producing a corresponding output signal. Decoders, adders, logic gates and shifters are examples of combinatorial logic networks. A simple exemplary decoder produces an output signal indicating the state of two input variables. Since there are four possible combinations of two binary input variables, the input state can be determined by a decoder capable of producing one of four output signals. The output signal thus indicates or decodes the input state. Combinatorial networks are conventionally built from basic logic circuits including AND gates, OR gates, inverters, etc.
Sequential logic circuits (or register logic circuits) produce an output signal in response to one or more input signals and a clock trigger signal. These synchronous circuits are typically constructed from basic flip-flops, that change state only at the active edge of a clock signal (where the active edge can be the leading clock edge or the lagging clock edge). Synchronous flip-flops and registers are examples of sequential networks. The clock signal synchronizes the operation of sequential networks by triggering registers and latches and advancing flip-flops.
Most conventional digital systems are designed to operate at a so-called full clock rate equal to the data rate. These synchronous circuits are triggered by the active edge of the clock signal. Each synchronous circuit has a known set up and hold time, representing the time during which the input signal must remain constant, both before and after the active clock edge, so that the circuit can perform its intended operation in response to the input signal. However, clock speeds are ever increasing in response to requirements for faster processing of digital data. As the period of each clock cycle decreases, there may be insufficient time for a circuit element (such as a gate) to perform its function during the interval between the active edge of two successive clock cycles. That is, when the clock period is less than the combined set up and hold time of a synchronous circuit element the output signal maybe erroneous.
To overcome this difficulty, circuit designers convert the full-rate digital design to a half-rate clock design. The half-rate design runs at half the original clock frequency (thus the clock period is doubled), but performs twice the number of data processing steps during each clock cycle, so that the output signals are equivalent to and occur at the same time as the full-rate design. To perform at the doubled rate, the half-rate design typically includes twice the number of circuit elements as the full-rate circuit, including both the registered or sequential logic elements and the non-registered or combinatorial logic elements.
The conversion process from the full rate to the half-rate design can be a time consuming task Control circuits or other circuits having a considerable number of full-rate feedback paths can be difficult to convert to a half-rate system. For example, converting a full-rate state machine to half-rate operation is a complex and time-consuming process, since there are a plurality of states and each state has several feed-forward paths. Doubling the circuit elements so that operation at half-rate produces output signals that are time-coincident with a full rate clock must account for these various states and their feed forward paths to the next state.
The conversion process is essentially ad hoc, relying primarily on the skill level and knowledge of the circuit designer. Thus the results of the conversion process often vary considerably in terms of the circuit area consumed on an integrated circuit device in which the design is implemented, power consumption, and overall effectiveness of the half-rate design when compared with its full-rate counterpart.